View ADL551308_4787171.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 MHz to 4 GHz, 80 dB Logarithmic Detector/Controller ADL5513
FEATURES
Wide bandwidth: 1 MHz to 4 GHz 80 dB dynamic range (3 dB) Constant dynamic range over frequency Stability over -40oC to +85oC temperature range: 0.5 dB Operating temperature range: -40oC to +125oC Sensitivity: -70 dBm Low noise measurement/controller output (VOUT) Pulse response time: 21 ns/20 ns (fall/rise) Single-supply operation: 2.7 V to 5.5 V @ 31 mA Power-down feature: 1 mW @ 5 V Small footprint LFCSP Fabricated using high speed SiGe process
FUNCTIONAL BLOCK DIAGRAM
NC
16
NC
15
CLPF
14
NC
13
DET VPOS 1 INHI 2
DET
DET
DET
DET
I
V
12 VOUT
I INLO 3
V
11 VSET
ADL5513
VPOS 4 SLOPE CONTROL
5 6
10 COMM
BAND GAP REFERENCE
7
GAIN BIAS
8
9 TADJ
07514-001
NC
NC
NC
NC
Figure 1.
APPLICATIONS
RF transmitter power amplifier linearization and gain/power control Power monitoring in radio link transmitters RSSI measurement in base stations, WLAN, WiMAX, RADAR
GENERAL DESCRIPTION
The ADL5513 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The ADL5513 maintains accurate log conformance for signals up to 4 GHz. The input dynamic range is typically 80 dB (referred to 50 ) with error less than 3 dB and 74 dB with error less than 1 dB. The ADL5513 has 20 ns response time that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 2.7 V to 5.5 V is required to power the device. Current consumption is 31 mA, and it decreases to 200 A when the device is disabled. The ADL5513 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier output to a magnitude corresponding to VSET. The ADL5513 provides 0 V to (VPOS - 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that increases linear-in-dB with RF input signal amplitude. The logarithmic slope is 21 mV/dB, determined by the VSET interface. The intercept is -88 dBm (referred to 50 , continuous wave input, 900 MHz) using the INHI input. These parameters are very stable against supply and temperature variations. The ADL5513 is fabricated on a SiGe bipolar IC process and is available in a 3 mm x 3 mm, 16-lead LFCSP package for the -40C to +125C operating temperature range. A fully populated evaluation board is available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADL5513 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Applications Information .............................................................. 14 Basic Connections ...................................................................... 14 Input Signal Coupling ................................................................ 14 Output Filtering .......................................................................... 14 Output Interface ......................................................................... 15 Setpoint Interface ....................................................................... 15 Description of Characterization ............................................... 15 Error Calculations ...................................................................... 16 Adjusting Accuracy Through Choice of Calibration Points............................................................................................ 16 Temperature Compensation of Output Voltage ..................... 17 Device Calibration ..................................................................... 18 Power-Down Functionality ....................................................... 18 Measurement Mode ................................................................... 19 Setting the Output Slope in Measurement Mode .................. 19 Controller Mode ......................................................................... 20 Constant Power Operation ....................................................... 20 Increasing the Dynamic Range of the ADL5513 ................... 22 Evaluation Board ............................................................................ 23 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5513 SPECIFICATIONS
VS = 5 V, TA = 25C, Z0 = 50 , Pin INHI and Pin INLO are ac-coupled, continuous wave (CW) input, single-ended input drive, VOUT tied to VSET, error referred to best-fit line (linear regression -20 to -40 dBm), unless otherwise noted. (Temperature adjust voltage optimized for 85C.) Table 1.
Parameter OVERALL FUNCTION Maximum Input Frequency FREQUENCY = 100 MHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C Conditions Min 1 PIN = -10 dBm PIN = -50 dBm 1.50 0.64 1.63 0.79 75 64 58 6 -58 0.27 0.003 -0.14 +0.15/-0.33 +0.23/-0.43 0.8 +0.12/-0.31 0.31 +0.74 +0.35/-0.18 +0.25/-0.47 +0.52/-0.24 21 -87 1.3/0.4 1.64 0.79 76 70 68 8 -62 0.2 0.002 0.34 +0.25/-0.3 +0.2/-0.53 +0.72/-0.1 +0.2/-0.3 +0.28/-0.37 0.7 +0.4/-0.36 +0.37/-0.5 +0.67/-0.28 Typ Max 4000 1.76 0.94 Unit MHz V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB mV/dB dBm k/pF V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm +25C < TA < +85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm 19.5
Logarithmic Slope Logarithmic Intercept Input Impedance FREQUENCY = 900 MHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C
22.5
PIN = -10 dBm PIN = -50 dBm
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm 25C < TA < 85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm
Rev. 0 | Page 3 of 28
ADL5513
Parameter Logarithmic Slope Logarithmic Intercept Input Impedance FREQUENCY = 1900 MHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C Conditions Min Typ 21 -88 1.3/0.4 1.66 0.80 75 70 68 8 -62 0.25 0.0012 0.52 +0.14/-0.41 +0.19/-0.51 0.9 +0.1/-0.38 +0.37/-0.26 0.83 +0.55/-0.3 +0.79/-0.16 +0.62/-0.41 21 -88 0.6/0.5 1.66 0.82 77 70 66 8 -62 0.33 0.02 0.23 0.28 +0.2/-0.52 +0.7/-0.1 +0.15/-0.35 +0.24/-0.41 0.77 +0.2/-0.6 +0.1/-0.94 +0.8/-0.2 21 -89 0.5/0.5 Max Unit mV/dB dBm k/pF V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB mV/dB dBm k/pF V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB mV/dB dBm k/pF
PIN = -10 dBm PIN = -50 dBm
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm 25C < TA < 85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm
Logarithmic Slope Logarithmic Intercept Input Impedance FREQUENCY = 2140 MHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C
PIN = -10 dBm PIN = -50 dBm
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm 25C < TA < 85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm
Logarithmic Slope Logarithmic Intercept Input Impedance
Rev. 0 | Page 4 of 28
ADL5513
Parameter FREQUENCY = 2600 MHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C Conditions PIN = -10 dBm PIN = -50 dBm Min Typ 1.67 0.83 80 74 69 7 -67 0.33 0.02 0.01 +0.2/-0.4 +0.05/-0.68 +0.75/-0.05 +0.1/-0.37 +0.25/-0.4 0.8 +0.2/-0.6 0.5 1.13 21 -89 0.4/0.6 1.74 0.84 76 62 58 1 -61 0.43 -0.05 -0.14 +0.32/-0.28 +0.27/-0.54 +0.58/-0.21 +0.3/-0.22 +0.38/-0.33 +0.67/-0.05 +0.41/-0.37 +0.41/-0.62 +0.8/-0.18 22.5 -87 0.5/0.4 2 0.58 47.1 40 Max Unit V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB mV/dB dBm k/pF V V dB dB dB dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB mV/dB dBm k/pF V V dB/ V k
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm 25C < TA < 85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm
Logarithmic Slope Logarithmic Intercept Input Impedance FREQUENCY = 3.6 GHz Output Voltage: High Power Input Output Voltage: Low Power Input 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation at TA = 25C
PIN = -10 dBm PIN = -50 dBm
Deviation vs. Temperature
PIN = -10 dBm PIN = -30 dBm PIN = -50 dBm Deviation from output at TA = 25C 25C < TA < 85C; PIN = -10 dBm -40C < TA < +25C; PIN = -10 dBm 25C < TA < 125C; PIN = -10 dBm 25C < TA < 85C; PIN = -30 dBm -40C < TA < +25C; PIN = -30 dBm 25C < TA < 125C; PIN = -30 dBm 25C < TA < 85C; PIN = -50 dBm -40C < TA < +25C; PIN = -50 dBm 25C < TA < 125C; PIN = -50 dBm
Logarithmic Slope Logarithmic Intercept Input Impedance SETPOINT INPUT Nominal Range Logarithmic Scale Factor Input Impedance
Pin VSET Log conformance error 1 dB, RF input = 8 dBm Log conformance error 1 dB, RF input = -62 dBm
Rev. 0 | Page 5 of 28
ADL5513
Parameter OUTPUT INTERFACE Voltage Swing Capacitance Drive Capacitance Drive Current Source/Sink Output Noise Conditions Pin VOUT VSET = 0 V, RF input = open VSET = 0.47 V, RF input = open CLPF = open CLPF = 20 pF Output held at 1 V to 1% change RF input = 100 MHz, 0 dBm fNOISE = 100 kHz, CLPF = open fNOISE = 100 kHz, CLPF = 1 nF Input level = no signal to 0 dBm, 90% to 10% CLPF = open, 1 s pulse width CLPF = open, 500 s pulse width CLPF = open, 1 s pulse width CLPF = open, 500 s pulse width CLPF = 1000 pF, 10 s pulse width CLPF = 1000 pF, 500 s pulse width CLPF = 1000 pF, 10 s pulse width CLPF = 1000 pF, 500 s pulse width CLPF = open, 3 dB video bandwidth Pin TADJ 0 to 1.3 VPOS - 0.3 31 200 V V mA A Min Typ 0.47 4.7 47 1 0.64/55 145 82 21 5.5 20 20 4.2 5.5 3.2 4.3 10 Max Unit V V pF nF mA nV/Hz nV/Hz ns s ns ns s s s s MHz
PULSE RESPONSE TIME Fall Time Rise Time Fall Time Rise Time Small Signal Video Bandwidth (or Envelope Bandwidth) TEMPERATURE ADJUST/POWER-DOWN INTERFACE Temperature Adjust Useful Range Minimum Logic Level to Disable Input Current Enable Time
Disable Time
Input Impedance 1 POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Supply Current
1
Logic high disables Logic high TADJ = 0 V Logic low TADJ = 4.7 V PWDN low to VOUT at 100% final value, PWDN high to VOUT at 10% final value CLPF = open, RF input = 0 dBm, 100 MHz, 1 s pulse width CLPF = 1000 pF, RF input = 0 dBm, 100 MHz, 1 s pulse width CLPF = open, RF input = 0 dBm, 100 MHz, 1 s pulse width CLPF = 1000 pF, RF input = 0 dBm, 100 MHz, 1 s pulse width TADJ = 0.9 V, sourcing 70 A Pin VPOS 2.7 25C, RF input = -55 dBm When disabled
84 10.8 165 1.2 13 5.5 31 <0.2
ns s ns s k V mA mA
See the Temperature Compensation of Output Voltage section.
Rev. 0 | Page 6 of 28
ADL5513 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage, VPOS VSET Voltage Input Power (Single-Ended, Re: 50 ) Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 0 V to VPOS 20 dBm 220 mW 79.3C/W 150C -40C to +125C -65C to +150C 260C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 7 of 28
ADL5513 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14 CLPF
PIN 1 INDICATOR
15 NC
16 NC
13 NC
VPOS 1 INHI 2 INLO 3 VPOS 4
12 VOUT 11 VSET 10 COMM 9 TADJ
ADL5513
TOP VIEW (Not to Scale)
NC 5
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO COMM; SOLDER TO A LOW IMPEDANCE GROUND PLANE.
NC 7
NC 6
NC 8
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 4 2 3 5, 6, 7, 8, 13, 15, 16 9 10 11 12 14 15 (EPAD) Mnemonic VPOS INHI INLO NC TADJ COMM VSET VOUT CLPF Exposed Paddle (EPAD) Description Positive Supply Voltage, 2.7 V to 5.5 V. RF Input. AC-coupled RF input. RF Common for INHI. AC-coupled RF common. No Connect. These pins can be left open or be soldered to a low impedance ground plane. Temperature Compensation Adjustment. Frequency-dependent temperature compensation is set by applying a specified voltage to the pin. The TADJ pin has dual functionality as a power-down pin, PWDN. Applying a voltage of VPOS - 0.3 V disables the device. Device Common. Setpoint Input for Operation in Controller Mode. To operate in RSSI mode short VSET to VOUT. Logarithmic/Error Output. Loop Filter Capacitor Pin. In measurement mode, this capacitor pin sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Internally connected to COMM; solder to a low impedance ground plane.
Rev. 0 | Page 8 of 28
07514-002
ADL5513 TYPICAL PERFORMANCE CHARACTERISTICS
VPOS = 5 V; TA = +25C, -40C, +85C, +125C; CLPF = 0.1 F, error is calculated by using the best-fit line between PIN = -20 dBm and PIN = -40 dBm at the specified input frequency, unless otherwise noted.
2.4 2.2 2.0 1.8 1.6
3.0 2.5 2.0 1.5 1.0
2.4 2.2 2.0 1.8 1.6
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C +125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0
07514-005 07514-010
ERROR (dB)
VOUT (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 +25C -40C +85C +125C 0
0 -0.5 -1.0 -1.5 -2.0 -2.5
VOUT (V)
1.4
0.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
Figure 3. VOUT and Log Conformance vs. Input Amplitude at 100 MHz, Typical Device, VTADJ = 0.89 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0
07514-003
-3.0 10
0 -70
-3.0 10
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz, Multiple Devices, VTADJ = 0.89 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C +125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0
07514-006
ERROR (dB)
VOUT (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 +25C -40C +85C +125C 0
0 -0.5 -1.0 -1.5 -2.0 -2.5
VOUT (V)
1.4
0.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
Figure 4. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Typical Device, VTADJ = 0.86 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0
07514-004
-3.0 10
0 -70
-3.0 10
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Multiple Devices, VTADJ = 0.86 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C 125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -3.0 10
ERROR (dB)
VOUT (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) +25C -40C +85C +125C -10 0
0 -0.5 -1.0 -1.5 -2.0 -2.5
VOUT (V)
1.4
0.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
Figure 5. VOUT and Log Conformance vs. Input Amplitude at 1900 MHz, Typical Device, VTADJ = 0.80 V
07514-007
-3.0 10
0 -70
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1900 MHz, Multiple Devices, VTADJ = 0.80 V
Rev. 0 | Page 9 of 28
ERROR (dB)
ERROR (dB)
ERROR (dB)
ADL5513
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C 125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0
07514-011 07514-016
ERROR (dB)
VOUT (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 +25C -40C +85C 125C 0
0 -0.5 -1.0 -1.5 -2.0 -2.5
VOUT (V)
1.4
0.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz, Typical Device, VTADJ = 0.84 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0
07514-008
-3.0 10
0 -70
-3.0 10
Figure 12. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz, Multiple Devices, VTADJ = 0.84 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C 125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0
07514-012
ERROR (dB)
VOUT (V)
VOUT (V)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 +25C -40C +85C 125C 0
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
Figure 10. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz, Typical Device, VTADJ = 0.83 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0
07514-009
-3.0 10
0 -70
-3.0 10
Figure 13. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz, Multiple Devices, VTADJ = 0.83 V
2.4 2.2 2.0 1.8 1.6 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C 125C -1.5 -2.0 -2.5 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -3.0 10
ERROR (dB)
VOUT (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 +25C -40C +85C 125C 0
0 -0.5 -1.0 -1.5 -2.0 -2.5
VOUT (V)
1.4
0.5
1.4 1.2 1.0 0.8 0.6 0.4 0.2
07514-013
-3.0 10
0 -70
Figure 11. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz, Typical Device, VTADJ = 0.90 V
Figure 14. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz, Multiple Devices, VTADJ = 0.90 V
Rev. 0 | Page 10 of 28
ERROR (dB)
ERROR (dB)
ERROR (dB)
ADL5513
100k
100k
PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -40dBm PIN = -60dBm PIN = OFF
NOISE SPECTRAL DENSITY (nV/ Hz)
NOISE SPECTRAL DENSITY (nV/ Hz)
10k
10k
PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -40dBm PIN = -60dBm PIN = OFF
1k
1k
100
100
07514-015
10k
100k FREQUENCY (Hz)
1M
10M
10k
100k FREQUENCY (Hz)
1M
10M
Figure 15. Output Noise Spectral Density, CLPF = Open
2.4 2.2 2.0 1.8 1.6 RF PULSE PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -30dBm PIN = -40dBm PIN = -50dBm PIN = -60dBm 6
Figure 18. Output Noise Spectral Density, CLPF = 1 nF
2.4 2.2
5
6
2.0 1.8
RF PULSE PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -30dBm PIN = -40dBm PIN = -50dBm PIN = -60dBm
5
INPUT PULSE (V)
VOUT (V)
VOUT (V)
1.4 1.2 1.0 0.8 0.6 0.4 0.2
1.4 1.2 1.0 0.8 0.6
3
3
2
2
1
0.4 0.2
07514-019
1
0
10
20
30
40 50 TIME (ms)
60
70
TIME (ns)
Figure 16. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency = 100 MHz, CLPF = Open
1.8 1.6 1.4 1.2 POWER-DOWN PULSE PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -30dBm PIN = -40dBm PIN = -50dBm PIN = -60dBm 4 5
Figure 19. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency = 100 MHz, CLPF = 0.1 F
1.8 1.6 1.4 4 POWER-DOWN PULSE PIN = 0dBm PIN = -10dBm PIN = -20dBm PIN = -30dBm PIN = -40dBm PIN = -50dBm PIN = -60dBm 5
POWER-DOWN PULSE (V)
1.2
VOUT (V)
VOUT (V)
1.0 0.8 0.6 0.4 0.2 0
3
1.0 0.8 0.6 0.4 0.2 0
3
2
2
1
1
07514-022
0
TIME (s)
TIME (s)
Figure 17. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency = 100 MHz, CLPF = Open
Figure 20. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency = 100 MHz, CLPF = 10 pF
Rev. 0 | Page 11 of 28
07514-021
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
900
-0.2
0
-0.2
0
POWER-DOWN PULSE (V)
07514-020
0 100 200 300 400
500 600
700
800
900 1000 1100 1200 1300
1400
1500 1600 1700
1800 1900
2000
0
0
0
0 80
INPUT PULSE (V)
4
1.6
4
07514-018
10 1k
10 1k
ADL5513
2.4 2.2 2.0 1.8 1.6 3.0 2.5
1600 MEAN = 21.0268 1400
2.0 1.5 1.0
1200 1000
VOUT (V)
COUNT
1.4 1.2 1.0 0.8 0.6 0.4 0.2 +25C -40C +85C +125C 0
0.5 0 -0.5 -1.0 -1.5 -2.0
ERROR (dB)
800 600 400 200
-2.5
07514-017
0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
20.0 20.5 21.0 21.5 22.0 SLOPE @ 5V/100MHz @ 25C (mV/dB)
22.5
Figure 21. Output Voltage Stability vs. Input Amplitude at 1900 MHz When VPOS Varies from 2.7 V to 5.5 V
Figure 23. Slope Distribution, 100 MHz
j1 j0.5 j2
100MHz 0 1/3 1 3 900MHz 1900MHz 2140MHz 2600MHz
3600MHz -j1
Figure 22. Input Impedance vs. Frequency, No Termination Resistor on INHI, Z0 = 50
07514-014
-j0.5
-j2
Rev. 0 | Page 12 of 28
07514-056
-3.0 5 10
0 19.5
ADL5513 THEORY OF OPERATION
The ADL5513 is a demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 4 GHz. A block diagram is shown in Figure 24. Sharing much of its design with the AD8313 logarithmic detector/controller, the ADL5513 maintains tight intercept variability vs. temperature over a 80 dB range. Additional enhancements over the AD8313, such as a reduced RF burst response time of 20 ns and board space requirements of only 3 mm x 3 mm, add to the low cost and high performance benefits found in the ADL5513.
NC
16
The logarithmic function is approximated in a piecewise fashion by cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, see the AD8307 data sheet.) Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high, due to the cascaded nature of the gain stages. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. After the detector currents are summed and filtered, the following function is formed at the summing node: ID x log10(VIN/VINTERCEPT) (1) where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage is 0 V, if it were capable of going to 0).
NC
15
CLPF
14
NC
13
DET VPOS 1 INHI 2
DET
DET
DET
DET
I
V
12 VOUT
I INLO 3
V
11 VSET
ADL5513
VPOS 4 SLOPE CONTROL
5 6
10 COMM
BAND GAP REFERENCE
7
GAIN BIAS
8
9 TADJ
07514-024
NC
NC
NC
NC
Figure 24. Block Diagram
A fully differential design, using a proprietary, high speed SiGe process, extends high frequency performance. The maximum input with 1 dB log conformance error is typically 10 dBm (referred to 50 ). The noise spectral density of -70 dBm sets the lower limit of the dynamic range. The common pin, COMM, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMM pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB.
Rev. 0 | Page 13 of 28
ADL5513 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5513 is specified for operation up to 4 GHz; as a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage of between 2.7 V and 5.5 V should be applied to VPOS. Connect 100 pF and 0.1 F power supply decoupling capacitors close to this power supply pin.
VPOS C3 0.1F C4 100pF C1 47nF VPOS 1
While the input can be reactively matched, in general, this is not necessary. An external 52.3 shunt resistor (connected to the signal side of the input coupling capacitors, as shown in Figure 25) combines with relatively high input impedance to give an adequate broadband 50 match. The coupling time constant, 50 x CC/2, forms a high-pass corner with a 3 dB attenuation at fHP = 1/(2 x 50 x CC ), where C1 = C2 = CC. Using the typical value of 47 nF, this high-pass corner is ~68 kHz. In high frequency applications, fHP should be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This low-pass filter network should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency.
R11 0
(SEE NOTE 1)
CLPF 14
NC 16
NC 15
NC 13
12
VOUT R4 0
VOUT
RFIN R1 52.3
2 INHI C2 47nF C5 100pF R12 0 C6 0.1F VPOS
VSET 11
ADL5513
COMM 10 9 TADJ (SEE NOTE 2)
3 INLO VPOS 4
6 NC
5 NC
7 NC
8 NC
OUTPUT FILTERING
For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the CLPF pin be left unconnected and free of any stray capacitance. The output video bandwidth, which is 10 MHz, can be reduced by connecting a ground-referenced capacitor (CFLT) to the CLPF pin, as shown in Figure 27. This is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals).
ILOG +4 1k 3pF VOUT CLPF CFLT
07514-027
Z1
Figure 25. Basic Connections
The exposed paddle of the LFCSP package is internally connected to COMM. For optimum thermal and electrical performance, solder the paddle to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled. INLO (input common) should be ac-coupled to ground. Suggested coupling capacitors are 47 nF, ceramic, 0402-style capacitors for input frequencies of 1 MHz to 4 GHz. The coupling capacitors should be mounted close to the INHI and INLO pins. The coupling capacitor values can be increased to lower the high-pass cutoff frequency of the input stage. The highpass corner is set by the input coupling capacitors and the internal 20 pF high-pass capacitor. The dc voltage on INHI and INLO is about one diode voltage drop below VPOS.
VPOS 7k 20pF 7k
07514-025
NOTES 1. SEE THE OUTPUT FILTERING SECTION. 2. SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE AND POWER-DOWN FUNCTIONALITY SECTIONS.
Figure 27. Lowering the Postdemodulation Bandwidth
CFLT is selected by
C FLT =
(2 x 1.5 k x Video Bandwidth) - 3.0 pF
1
The video bandwidth should typically be set to a frequency equal to about one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. In many log amp applications, it may be necessary to lower the corner frequency of the postdemodulation filter to achieve low output ripple while maintaining a rapid response time to changes in signal level. An example of a four-pole active filter is shown in the AD8307 data sheet. Averaging the output measurement can also be done when filtering is not possible.
15k INHI
15k GAIN STAGE
2k INLO
OFFSET COMP
Figure 26. Input Interface
Rev. 0 | Page 14 of 28
07514-026
gm
ADL5513
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal 10 resistor is placed in series with the output and the VOUT pin. The rise time of the output is limited mainly by the slew on CLPF. The fall time is an RC-limited slew given by the load capacitance and the pull-down resistance at VOUT. There is an internal pull-down resistor of 1.6 k. A resistive load at VOUT is placed in parallel with the internal pull-down resistor to provide additional discharge current.
VPOS CLPF 10 0.8V + - 1200
07514-028
VSET
20k
VSET ISET
20k
COMM
COMM
Figure 29. VSET Interface
VOUT
The slope is given by ID x 2x x 3.5 k = 20 mV/dB x x. For example, if a resistor divider to ground is used to generate a VSET voltage of VOUT/2, then x = 2. The slope is set to 800 V/decade or 40 mV/dB. See the Measurement Mode section for more information on setting the slope in measurement mode.
DESCRIPTION OF CHARACTERIZATION
The general hardware configuration used for most of the ADL5513 characterization is shown in Figure 30. The signal source and power supply used in this example are the Agilent E8251A PSG signal generator and E3631A triple output power supply. Output voltage was measured using the Agilent 34980A switch box.
AGILENT E3631A TRIPLE OUTPUT POWER SUPPLY AGILENT E8251A PSG SIGNAL GENERATOR VPOS
400 COMM
Figure 28. Output Interface
The ADL5513 output can drive over 1 nF of capacitance. When driving such high output capacitive loads, it is required to capacitively load the CLPF pin. The capacitance on the CLPF pin should be at least 1/50th that of the capacitance on the VOUT pin.
SETPOINT INTERFACE
The VSET input drives the high impedance (40 k) input of an internal op amp. The VSET voltage appears across the internal 3.5 k resistor to generate ISET. When a portion of VOUT is applied to VSET, the feedback loop forces ID x log10(VIN/VINTERCEPT) = ISET If VSET = VOUT/2x, ISET = VOUT/(2x x 3.5 k). The result is VOUT = (ID x 3.5 k x 2x) x log10(VIN/VINTERCEPT). (2)
ADL5513
INHI INLO CHARACTERIZATION BOARD
VOUT
AGILENT 34980A SWITCH BOX
07514-029
3.5k
CONTROLLING COMPUTER
Figure 30. General Characterization Configuration
Rev. 0 | Page 15 of 28
07514-030
ADL5513
ERROR CALCULATIONS
The measured transfer function of the ADL5513 at 100 MHz is shown in Figure 31. The figure shows plots of measured output voltage, calculated error, and an ideal line. The input power and output voltage are used to calculate the slope and intercept values. The slope and intercept are calculated using linear regression over the input range from -40 dBm to -20 dBm. The slope and intercept terms are used to generate an ideal line. The error is the difference in measured output voltage compared to the ideal output line.
2.4 2.2 2.0 1.8 1.6
VOUT (V)
Figure 31 shows a plot of the error at 25C, the temperature at which the device is calibrated. Error is not 0 dB over the full dynamic range. This is because the log amp does not perfectly follow the ideal VOUT vs. PIN equation, even within its operating range. The error at the calibrating points of -20 dBm and -40 dBm is equal to 0 dB by definition. Figure 31 also shows error plots for output voltages measured at -40C and 85C. These error plots are calculated using slope and intercept at 25C, which is consistent in a mass-production environment, where calibration over temperature is not practical. This is a measure of the linearity of the device. Error from the linear response to the CW waveform is not a measure of absolute accuracy because it is calculated using the slope and intercept of each device. However, error verifies the linearity of the devices. Similarly, at temperature extremes, error represents the output voltage variations from the 25C ideal line performance. Data presented in the graphs are the typical error distributions observed during characterization of the ADL5513. Device performance was optimized for operation at 85C; this can be changed by changing the voltage at TADJ.
3.0 IDEAL LINE VOUT AND ERROR @ +25C VOUT AND ERROR @ -40C VOUT AND ERROR @ +85C VOUT1 2.5 2.0 1.5 1.0 0.5 VOUT2 0 -0.5 -1.0 -1.5 -2.0 -2.5 PIN2
-60 -55 -50 -45 ERROR (dB)
1.4 1.2 1.0 0.8 0.6 0.4 0.2
-5 0
07514-031
-90 -85
-80 -75 -70 -65
-40 -35 -30 -25
-20 -15
-10
5 10
0
PIN1
-3.0
ADJUSTING ACCURACY THROUGH CHOICE OF CALIBRATION POINTS
Choose calibration points to suit the specific application, but usually they should be in the linear range of the log amp. In some applications, very high accuracy is required at a reduced input range; in other applications, good linearity is necessary over the full power input range. The linearity of the transfer function can be adjusted by choice of calibration points. Figure 32 and Figure 33 show plots for a typical device at 3600 MHz as an example of adjusting accuracy through choice of calibration points.
2.50 2.25 2.00 1.75 2.5 2.0 1.5 1.0 0.5 0 -0.5 +25C -40C +85C +125C -1.0 -1.5 -2.0
07514-032
PIN (dBm)
Figure 31. Typical Output Voltage vs. Input Signal
The equation for output voltage can be written as VOUT = Slope x (PIN - Intercept) where: Slope is the change in output voltage divided by the change in input power, PIN. Slope is expressed in volts per decibel (V/dB). Intercept is the calculated power in decibels (dB) at which the output voltage is 0 V. Note that VOUT = 0 V can never be achieved. Calibration is performed by applying two known signal levels to the ADL 5513 and measuring the corresponding voltage outputs. The calibration points are in general chosen to be within the linear-in-dB range of the device. Calculation of the slope and intercept are accomplished by using the following equations:
VOUT (V)
1.50 1.25 1.00 0.75 0.50 0.25 0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
VOUT ( MEASURED )1 VOUT ( MEASURED ) 2 Slope PIN1 PIN2
Intercept PIN1 VOUT ( MEASURED ) Slope
0
-2.5 5 10
Once the slope and intercept are calculated, VOUT(IDEAL) can be calculated, and the error is determined using the following equation:
Figure 32. Typical Device at 3600 MHz, Calibration Points at PIN = -20 dBm and -40 dBm
Error
(VOUT ( MEASURED ) VOUT ( IDEAL)) Slope
Rev. 0 | Page 16 of 28
ERROR (dB)
ADL5513
2.50 2.25 2.00 1.75 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 +25C -40C +85C +125C 0 -1.5 -2.0
07514-033
improve linearity and extend the dynamic range, unless enough calibration points are used to remove error. Figure 34 is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) output voltage at ambient.
VOUT (V)
1.50 1.25 1.00 0.75 0.50 0.25 0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
ERROR (dB)
TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE
The primary component of the variation in VOUT vs. temperature as the input signal amplitude is held constant is the drift of the intercept. This drift is also a weak function of the input signal frequency; therefore, a provision is made for the optimization of the internal temperature compensation at a given frequency by providing Pin TADJ with dual functionality. The first function for this pin is temperature compensation and the second function is to power down the device when VTADJ = VPOS - 0.3 V (see the Power-Down Functionality section).
VINTERNAL ICOMP PWDN/TADJ
-2.5 5 10
Figure 33. Typical Device at 3600 MHz, Calibration Points at PIN = -12 dBm and -40 dBm
In Figure 32, calibration points are chosen so that linearity is improved over the full dynamic range, but error at the higher power level at PIN = -10 dBm is 0.5 dB at 25C. In Figure 33, calibration points are chosen so that error is smaller at higher power input ,but with loss of linearity over the full dynamic range. Figure 34 shows another way of presenting the error of a log amp detector. The same typical device from Figure 32 and Figure 33 is presented where the error at -40C, +85C, and +125C are calculated with respect to the output voltage at +25C. This is the key difference in presenting the error of a log amp compared with the plots in Figure 32 and Figure 33 where the error is calculated with respect to the ideal line at 25C.
2.50 2.25 2.00 1.75 -40C +85C +125C 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
07514-034
COMM
COMM
Figure 35. TADJ Interface
VTADJ is a voltage forced between TADJ and ground. The value of this voltage determines the magnitude of an analog correction coefficient, which is used to reduce intercept drift. The relationship between output temperature drift and frequency is not linear and cannot be easily modeled. As a result, experimentation is required to select the optimum VTADJ voltage. The VTADJ voltage applied to Pin TADJ can be supplied by a DAC with sufficient resolution, or Resistor R8 and Resistor R9 on the evaluation board (see Figure 47) can be configured as a voltage divider using VPOS as the voltage source. Table 4 shows the recommended voltage values for some commonly used frequencies in characterization to optimize operation at 85C. The TADJ pin has high input impedance. Table 4. Recommended VTADJ Values
Frequency 100 MHz 900 MHz 1.9 GHz 2.14 GHz 2.6 GHz 3.6 GHz Recommended VTADJ (V) 0.89 0.86 0.80 0.84 0.83 0.90
VOUT (V)
1.50 1.25 1.00 0.75 0.50 0.25 0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
0
-2.5 5 10
Figure 34. Error vs. Temperature with Respect to Output Voltage at 25C, 3600 MHz
With this alternative technique, the error at ambient becomes 0 dB by definition. This would be valid if the device transfer function perfectly followed the ideal equation or if there were many calibration points used. VOUT = Slope x (PIN - Intercept) Because the log amp never perfectly follows this equation, especially outside of its linear range, Figure 34 can be misleading as a representation of log amp error. This plot tends to artificially
Rev. 0 | Page 17 of 28
ERROR (dB)
07514-035
ADL5513
Compensating the device for temperature drift using TADJ allows for great flexibility. If the user requires minimum temperature drift at a given input power or subset of the dynamic range, the TADJ voltage can be swept while monitoring VOUT over temperature. Figure 36 shows how error changes on a typical part over the full dynamic range when VTADJ is swept from 0.5 V to 1.2 V in steps of 0.1 V.
2.4 2.2 2.0 1.8 1.6 VTADJ = 0.5V 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 VTADJ = 1.2V +25C +85C 0 -1.5 -2.0 -2.5
07514-036
1.5 +25C 0C +85C 1.0 -40C +45C +105C -20C +65C +125C
ERROR (dB), PIN = -30dBm
0.5
0
-0.5
VOUT (V)
1.4 1.2 1.0 0.8 0.6 0.4 0.2
ERROR (dB)
0.6
0.7
0.8 0.9 TADJ (V)
1.0
1.1
1.2
Figure 37. Error vs. VTADJ, PIN = -30 dBm at 1900 MHz
It is important that temperature adjustment be performed on multiple devices.
POWER-DOWN FUNCTIONALITY
Power-down functionality of ADL5513 is achieved through externally applied voltage on the TADJ pin. If VTADJ = VPOS - 0.3 V, the output voltage and supply current are close to 0.
1.8 1.6 1.4 +25C -40C +85C +125C
0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
-3.0 5 10
Figure 36. VOUT vs. TADJ at 85C, 1900 MHz
VOUT @ -10dBm (V)
Figure 37 shows the results of sweeping VTADJ over multiple temperatures while holding PIN constant. The same VTADJ should be used for the full dynamic range for a specified supply operation.
1.2 1.0 0.8 0.6 0.4 0.2
07514-038
DEVICE CALIBRATION
VTADJ voltages in Table 4 are chosen so that the error is at its minimum at 85C. Criteria for the choice of VTADJ is unique for a given application. Figure 37 shows how error on a typical device changes at INHI = -30 dBm when VTADJ is swept at different temperatures. If the ADL5513 must have minimum error at a certain temperature, then VTADJ should be chosen such that the line for that temperature intersects the 25C line. At this VTADJ setting, the error at all other temperatures is not the minimum. If the deviation of error over temperature is more important than the error at a single temperature, VTADJ should be determined by the intersection of the lines for the temperatures of interest. For the characterization data presented, VTADJ values were chosen so that ADL5513 has a minimum error at 85C, which is at the intersection of the lines for 85C and 25C. For example, at 1900 MHz, VTADJ = 0.8 V. If a given application requires error deviation to be at a minimum when the temperature changes from -40C to 85C, VTADJ is determined by the intersection of the error line for those temperatures.
0 4.0
4.1
4.2
4.3
4.4
4.5 4.6 TADJ (V)
4.7
4.8
4.9
5.0
Figure 38. VOUT vs. VTADJ at 100 MHz, VPOS = 5 V
100 +25C -40C +85C +125C
SLEEP CURRENT (mA)
10
1
4.1
4.2
4.3
4.4
4.5 4.6 TADJ (V)
4.7
4.8
4.9
5.0
Figure 39. Sleep Current vs. VTADJ, VPOS = 5 V
Rev. 0 | Page 18 of 28
07514-039
0.1 4.0
07514-037
-1.0 0.5
ADL5513
MEASUREMENT MODE
When the VOUT voltage or a portion of the VOUT voltage is fed back to the VSET pin, the device operates in measurement mode. As shown in Figure 40, the ADL5513 has an offset voltage, a positive slope, and a VOUT measurement intercept at the low end of its input signal range.
2.4 2.2 2.0 1.8 1.6 VOUT1 ERROR 25C 0.5 VOUT2 0 -0.5 -1.0 -1.5 -2.0 VOUT 25C PIN2 PIN1 -2.5 3.0 2.5 2.0 1.5 1.0
For example, PINTERCEPT for a sinusoidal input signal expressed in terms of decibels referred to 1 mW (dBm) in a 50 system is PINTERCEPT(dBm) = PINTERCEPT(dBV) - 10 x log10(Z0 x 1 mW/1 Vrms2) = -100 dBV - 10 x log10(50 x 10-3) = -87 dBm
(7)
Further information on the intercept variation dependence upon waveform can be found in the AD8313 and AD8307 data sheets.
SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE
To operate in measurement mode, VOUT is connected to VSET. Connecting VOUT directly to VSET yields the nominal logarithmic slope of approximately 20 mV/dB. The output swing corresponding to the specified input range is then approximately 0.47 V to 2.0 V. The slope and output swing can be increased by placing a resistor divider between VOUT and VSET (that is, one resistor from VOUT to VSET and one resistor from VSET to ground). The input impedance of VSET is approximately 40 k. Slope-setting resistors should be kept below 20 k to prevent this input impedance from affecting the resulting slope. If two equal resistors are used (for example, 10 k /10 k), the slope doubles to approximately 40 mV/dB.
ADL5513
VOUT 10k VSET 10k
07514-041
VOUT (V)
1.4 1.2 1.0 0.8
VOUT 0.6 IDEAL 0.4 0.2
-5 0
-90 -85
-80 -75 -70 -65
-60 -55
-50 -45
-40 -35 -30 -25
-20 -15
-10
5 10
0
-3.0
07514-040
PIN (dBm)
Figure 40. Typical Output Voltage vs. Input Signal
The output voltage vs. input signal voltage of the ADL5513 is linear-in-dB over a multidecade range. The equation for this function is VOUT = X x VSLOPE/DEC x log10(VIN/VINTERCEPT) = X x VSLOPE/dB x 20 x log10(VIN/VINTERCEPT) where: X is the feedback factor in VSET = VOUT/X. VSLOPE/DEC is nominally 400 mV/decade or 20 mV/dB. VINTERCEPT is the x-axis intercept of the linear-in-dB portion of the VOUT vs. PIN curve (see Figure 40). VINTERCEPT is -100 dBV for a sinusoidal input signal. An offset voltage, VOFFSET, of 0.47 V is internally added to the detector signal, so that the minimum value for VOUT is X x VOFFSET; therefore, for X = 1, the minimum VOUT is 0.47 V. The slope is very stable vs. process and temperature variation. When Base 10 logarithms are used, VSLOPE/DEC represents the volts per decade. A decade corresponds to 20 dB; VSLOPE/DEC/20 = VSLOPE/dB represents the slope in volts per decibel (V/dB). As shown in Figure 40, VOUT voltage has a positive slope. Although demodulating log amps respond to input signal voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. In this case, the characteristic impedance of the system, Z0, must be known to convert voltages to their corresponding power levels. The following equations are used to perform this conversion: P(dBm) = 10 x log10(Vrms2/(Z0 x 1 mW)) P(dBV) = 20 x log10(Vrms/1 Vrms) P(dBm) = P(dBV) - 10 x log10(Z0 x 1 mW/1 Vrms )
2
ERROR (dB)
40mV/dB
(3)
Figure 41. Increasing the Slope
The required resistor values needed to increase the slope are calculated from the following equation.
Slope2 R1 +1 = R2 Slope1
where: R1 is the resistor from VOUT to VSET. R2 is the resistor from VSET to ground. Slope1 is the nominal slope of the ADL5513. Slope2 is the new slope.
(8)
It is important to remember when increasing the slope of the ADL5513 that R1 and R2 must be properly sized so the output current drive capability is not exceeded. The dynamic range of the ADL5513 may be limited if the maximum output voltage is achieved before the maximum input power is reached. In cases where VPOS is 5 V, the maximum output voltage is 4.7 V. The slope of the ADL5513 can be reduced by connecting VSET to VOUT and adding a voltage divider on the output.
(4) (5) (6)
Rev. 0 | Page 19 of 28
ADL5513
CONTROLLER MODE
The ADL5513 provides a controller mode feature at Pin VOUT. Using VSET for the setpoint voltage, it is possible for the ADL5513 to control subsystems, such as power amplifiers (PAs), variable gain amplifiers (VGAs), or variable voltage attenuators (VVAs), which have output power that increases monotonically with respect to their gain control signal. To operate in controller mode, the link between VSET and VOUT is broken. A setpoint voltage is applied to the VSET input, VOUT is connected to the gain control terminal of the VGA, and the RF input of the detector is connected to the output of the VGA (usually using a directional coupler and some additional attenuation). Based on the defined relationship between VOUT and the RF input signal when the device is in measurement mode, the ADL5513 adjusts the voltage on VOUT (VOUT is now an error amplifier output) until the level at the RF input corresponds to the applied VSET. When the ADL5513 operates in controller mode, there is no defined relationship between the VSET and the VOUT voltage; VOUT settles to a value that results in the correct input signal level appearing at INHI/INLO. For this output power control loop to be stable, a groundreferenced capacitor must be connected to the CLPF pin. This capacitor, CFLT, integrates the error signal (in the form of a current) to set the loop bandwidth and ensure loop stability. Further details on control loop dynamics can be found in the AD8315 data sheet.
VGA/VVA DIRECTIONAL COUPLER RFIN
CONSTANT POWER OPERATION
In controller mode, the ADL5513 can be used to hold the output power stable over a broad temperature/input power range. This can be useful in topologies where a transmit card is driving an HPA or when connecting power-sensitive modules together. Figure 44 shows a schematic of a circuit setup that holds the output power to approximately -39 dBm at 900 MHz when the input power is varied over a 62 dB dynamic range. Figure 43 shows the performance results. A portion of the output power is coupled to the input of ADL5513 using a 20 dB coupler. The VSET voltage is set to 0.65 V, which forces the ADL5513 output voltage to control the ADL5330 to deliver -59 dBm. (If the ADL5513 is in measurement mode and a -59 dBm input power is applied, the output voltage is 0.65 V). A generic op amp is used (AD8062) to invert the slope of the ADL5513 so that the gain of the ADL5330 decreases as the ADL5513 control voltage increases. The high end power is limited by the maximum gain of the ADL5330 and can increase if VSET is moved so that the ADL5513 has a higher power on its input and a VGA with higher linearity is used. The low power is limited by the sensitivity of the ADL5513 and can be increased with a reduction in the coupling value of the coupler.
-35 -36 -37 -38
POUT (dBm)
-39 -40 -41 -42 -43 -44 +25C -40C +85C
07514-044
GAIN CONTROL VOLTAGE 47nF INHI VOUT
52.3
47nF
ADL5513
INLO VSET CLPF CFLT
07514-042
DAC
-45 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm)
0
5
Figure 43. Performance of ADL5330/ADL5513 Constant Power Circuit
Figure 42. Controller Mode
Rev. 0 | Page 20 of 28
ADL5513
GND
VPOS
5V 20k
0.1F
0.1uF
C7 1000pF 10k
5V
SW1
VPOS
100pF
CLPF 14
NC 16
NC 15
NC 13
SMA GAIN 0
0 0.1F 100pF 0
10k
5V
VPOS
47nF 52.3
1
12
VOUT 1k
10k
2 INHI
120nH 100pF
VSET 11
ADL5513
COMM 10 9
3 INLO
47nF
VSET = 0.65V 10k 5V 10k
AD8062
10k VPOS 0.1F 0 100pF
GAIN VPS2 VPS2 ENBL VPS2 VPS2
VPOS
4
DIRECTIONAL COUPLER 20dB
6 NC
5 NC
7 NC
8 NC
TADJ
VTADJ 100pF
Z1
120nH 100pF
VPS1
VPS2 COM2
INPUT
T1
100pF
COM1 INHI INLO
ADL5330
OPHI OPLO COM2 VPS2
T2
RFOUT 5V
0.1uF
100pF 5V 0.1F 0 100pF
COM1
100pF
COM1
VREF
IPBS
OPBS
COM2
GNLO
VPS1
100pF 0
1nF
1nF VPOS
Figure 44. Schematic of the ADL5513 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330
Rev. 0 | Page 21 of 28
07514-043
0.1F
ADL5513
INCREASING THE DYNAMIC RANGE OF THE ADL5513
The ADL5513 dynamic range can be extended by adding a standalone VGA, whose gain control input is derived directly from VOUT. This extends the dynamic range by the gain control range of the VGA. In order for the overall measurement to remain linear in dB, the VGA must provide a linear-in-dB (exponential) gain control function. The VGA gain must decrease with an increase in its gain bias in the same way as the ADL5513. Alternatively, an inverting op amp with suitable level shifting can be used. It is convenient to select a VGA that needs only a single 5.0 V supply and is capable of generating a single-ended output. All of these conditions are met by the AD8368. Figure 46 shows the schematic. Using the inverse gain mode (MODE pin low) of the AD8368, its gain decreases on a slope of 37.5 mV/dB to a minimum value of -12 dB for a gain voltage (VGAIN) of 1.0 V. The voltage, VGAIN, that is required by the AD8368 is 50% of the output of the ADL5513. To scale this voltage, it is necessary to install a voltage divider at the output of the ADL5513. Over the 1.5 V range from the output of the ADL5513, the gain of the AD8368 varies by (0.5 x 1.5 V)/(37.5 mV/dB), or 20 dB. Combined with the 75 dB gain span (at 120 MHz) of the ADL5513, this results in a 95 dB variation for a 1.5 V change in VOUT. Due to the amplification of out-of-band noise by AD8368, a band-pass filter was inserted between the AD8368 and ADL5513 to increase the low end sensitivity. The VGA amplifies low power signals and attenuates high power signals to fit them in the detectable range of the ADL5513. If an amplifier with higher gain and lower noise figure is used, better than 90 dB sensitivity can be achieved for use in an RSSI application. Figure 45 shows data results of the extended dynamic range at 120 MHz with error in VOUT.
1.750 1.625 1.500 1.375 1.250
VOUT (V)
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 VOUT +25C VOUT -40C VOUT +85C ERR0R +25C ERR0R -40C ERR0R +85C -80 -70 -60 -50 -40 -30 -20 PIN (dBm) -10 0 10 -1.0 -1.5 -2.0 -2.5
07514-045
1.125 1.000 0.875 0.750 0.625 0.500 0.375 0.250 -90
-3.0 20
Figure 45. Output and Conformance for the AD8368/ADL5513 Extended Dynamic Range Circuit
VPOS
VPOS
VPOS1 VPOS2 VPOS3
1nF
5.6pF
ICOM
ICOM
DECL
INPUT 10nF
DECL
VPSI
215
INPT
ICOM
VPOS2 0
VPSI VPSI
VPOS
VPOS
GND
10nH 10k VPOS1 0 0.1F C10 1nF
ICOM MODE VPSI VPSI
C12 1nF C12 1nF
C15 0.1F
0.1uF
VPOS3
C7 1000pF
AD8368
VPSO VPSO OUTP
CLPF 14
NC 16
NC 15
NC 13
10nF
0 C15 0.1F
100pF VPOS 47nF 52.3 VOUT 1k VOUT
DECL
OCOM
ENBL
OCOM
1
12
DETO
HPFL
GAIN
DETI
2 INHI
BAND-PASS 120MHz
3 INLO VPOS 4
ADL5513
VSET 11
10nF
1nF
COMM 10 9
6 NC
5 NC
7 NC
8 NC
TADJ VTADJ = 0.89V 1k
100pF
Z1
0.1uF VPOS 1k
07514-046
Figure 46. ADL5513 with 95 dB Dynamic Range
Rev. 0 | Page 22 of 28
ERROR (dB)
ADL5513 EVALUATION BOARD
GND VPOS C3 0.1F C4 100pF VPOS VOUT_ALT C7 1000pF R2 OPEN R11 0
CLPF 14
NC 16
NC 15
NC 13
RFIN R1 52.3
C1 47nF
VPOS 1
12
VOUT R4 0
R3 1k CL OPEN RL OPEN
VOUT
2 INHI C2 47nF
VSET 11
ADL5513
COMM 10 9 R5 OPEN
3 INLO VPOS 4
6 NC
5 NC
7 NC
8 NC
TADJ
R10 0 VSET
C5 100pF R12 0
Z1
VPOS TADJ R8 OPEN TADJ R9 OPEN
R6 OPEN C6 0.1F R7 0
VPOS EXT_PWDN_TADJ
07514-047
Figure 47. Evaluation Board Schematic
07514-048
Figure 48. Component Side Layout
Figure 49. Component Side Silkscreen
Rev. 0 | Page 23 of 28
07514-049
ADL5513
Table 5. Evaluation Board Configuration Options
Component C1, C2, R1 Function Input interface. The 52.3 resistor in Position R1 combines with the internal input impedance of the ADL5513 to give a broadband input impedance of about 50 . C1 and C2 are dc-blocking capacitors. A reactive impedance match can be implemented by replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors. Power supply decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the ADL5513 and a 0.1 F capacitor placed nearer to the power supply input pin. If additional isolation from the power supply is required, a small resistance (R11 or R12) can be installed between the power supply and the ADL5513. Filter capacitor. The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the ADL5513 for pulsed input signals. Output interface--measurement mode. In measurement mode, a portion of the output voltage is fed back to the VSET pin via R4. The magnitude of the slope of the VOUT output voltage response can be increased by reducing the portion of VOUT that is fed back to VSET. R3 can be used as a back-terminating resistor or as part of a single-pole, low-pass filter. If a reduction in slope is desired, a voltage divider can be installed at the output using R3 and RL. Output interface--controller mode. In controller mode, the ADL5513 can control the gain of an external component. To allow for this, remove the R4 resistor. A setpoint voltage is applied to Pin VSET. The value of this setpoint voltage corresponds to the desired RF input signal level applied to the ADL5513 RF input. A sample of the RF output signal from this variable gain component is applied to the ADL5513 input by a directional coupler. The voltage at the VOUT pin is applied to the gain control of the variable gain element. The magnitude of the control voltage can optionally be reduced via a voltage divider comprising R3 and RL, or a low-pass filter can be installed using R3 and CL. Temperature compensation interface. A voltage source can be used to optimize the temperature performance for various input frequencies. The pads for R8 and R9 can be used for a voltage divider from the VPOS node to set the TADJ voltage at different frequencies. The ADL5513 can be disabled by applying a voltage of VPOS - 0.3 V to this node. Default Value R1 = 52.3 (Size 0402) C1 = 47 nF (Size 0402) C2 = 47 nF (Size 0402)
C3, C4, C5, C6, R11, R12
C7
C3 = 0.1 F (Size 0402) C4 = 100 pF (Size 0402) C5 = 100 pF (Size 0402) C6 = 0.1 F (Size 0402) R11 = 0 (Size 0402) R12 = 0 (Size 0402) C7 = 1000 pF (Size 0402)
R2, R3 R4, R5, R10, RL, CL
R2 = open (Size 0402) R3 = 1 k (Size 0402) R4 = 0 (Size 0402) R5 = open (Size 0402) R10 = open (Size 0402) RL = CL = open (Size 0402) R2 = open (Size 0402) R3 = 1 k (Size 0402) R4 = open (Size 0402) R5 = open (Size 0402) R10 = 0 (Size 0402) RL = CL = open (Size 0402)
R6, R7, R8, R9
R6 = open (Size 0402) R7 = 0 (Size 0402) R8 = open (Size 0402) R9 = open (Size 0402)
Rev. 0 | Page 24 of 28
ADL5513 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
071708-A
0.60 MAX
BOTTOM VIEW
0.50 0.40 0.30
13 12
16
PIN 1 INDICATOR *1.65
1.50 SQ 1.35
1
EXPOSED PAD
9 8
4 5
0.25 MIN
1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5513ACPZ-R71 ADL5513ACPZ-R21 ADL5513ACPZ-WP1 ADL5513-EVALZ1
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-16-3 CP-16-3 CP-16-3
Branding Q1L Q1L Q1L
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
ADL5513 NOTES
Rev. 0 | Page 26 of 28
ADL5513 NOTES
Rev. 0 | Page 27 of 28
ADL5513 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07514-0-10/08(0)
Rev. 0 | Page 28 of 28

▲Up To Search▲

Price & Availability of ADL551308

	To Download ADL551308 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .